A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver

With the great increases in data transmission rate requirements, analog-to-digital converter (ADC)-based wireline receivers have received more and attention due to their flexible powerful equalization capabilities. Considering power consumption, baud-rate Mueller–Muller clock recovery (MM-CDR) circuits are widely used ADC-based since MM-CDR only need one sample signal per unit interval (UI). However, set an additional Vref voltage match size of main tap channel. If matching is not appropriate or quality good as a square wave, cannot accurately lock on certain phase instead drift within range. Therefore, robust stable oversampled CDR circuits. In this study, digital bang-bang (DBB-CDR) circuit combined with receiver was proposed. The DBB-CDR could eliminate various unstable factors achieve fast locking without excessively increasing consumption. A model actual 32 Gb/s receiver, which implemented 28 nm CMOS technology analyze performance circuit. simulation results showed that 0.42 UIpp JTOL@10MHz, minimum JTOL value 0.362 under 0.04 UI variance Gaussian jitter. area consumption were 64 μm2 0.02 mW, respectively; also obtain very demonstrated frequency offset tracking ability when there offset.